LSI programmable processor

ABSTRACT

A microprogrammable serial byte processor suitable for complete implementation of memory, logic, control and addressing functions on a single integrated circuit chip through large scale integration technology. An instruction set, at the microprogrammable level, is provided for controlling the processor in executing basic computer functions. Each instruction of the instruction set has a unique format which is decoded and executed by a circuit design that initially represents minimally committed logic or hardware, and which becomes committed to a specific task by control signals which are decoded from the formatted instructions. Specific circuitry for executing serially by bit the individual instructions of the instruction set is maintained at a simple and minimal level by employing a soft mechine architecture with a microprogramming approach.

I United States Patent 1 n 11 3,878,514

Faber Apr. 15, 1975 1 LS] PROGRAMMABLE PROCESSOR Primary Examiner-Harvey E. Springboi'n [75] Inventor: Ulbe Faber9 Hnmzybmokv Pu Attorney, Agent, orFu-m-Edmund M. Chung; Edward J. Feeriey, Jr.; Kevin R. Peterson [73] Assignee: Burroughs Corporation, Detroit,

Mich.

[57] ABSTRACT [22] Filed: Nov. 20, 1972 A microprogrammablc serial byte processor suitable {2!} Appl' 307363 for complete implementation of memory, logic, control and addressing functions on a single integrated [52] US. Cl. 340/l72.5 circu p through large Scale imegralio" wchnol' 51 Int. Cl. G06f 9/16 An instruction at the micropmgwmmable [58] Field of Search 340/1725 level is Provided for Controlling the processor in cutirig basic computer functions. Each instruction of [56] References Ci d the instruction set has a unique format which is de- UNITED STATES PATENTS coded and executed by a circuit design that initially 3302183 M B n t I 3 0/ 25 represents minimally committed logic or hardware. enne e a.

e1 3,700,873 lO/l972 Yhap 340N725 g 1736.567 5/1973 Lotan at al H 340N725 instructions. Specific circuitry for executing serially by 3.745533 7/1973 Erwin et al' 340/1715 bit the individual instructions of the instruction set is 3.760369 9/1973 Kemp 340/1715 maintained at a simple and minimal level by employ- 3,768,076 10/1973 Recoque 340/1725 ing a soft mechine architecture with a microprogramming approach.

9 Claims, 49 Drawing Figures I0 J DATA m LITERAL l [l2 MICROlNSl'RUCTION I a [8) 2) Q L WIE P: 0 TR 7 I f MICROPROBRAM gb l l MEMDRHMPM) I I f assailants" l l l I MlCRGADDRlESS FOR LU AND i4 EXTERNAL l l N5 8) l CONTROL i l 2 lTllglllROL CUNDllIDN I STING AND SETTING I l SS gg Jf F (LCLLCLLCZ) m m I i 3. DETERMINE ICONBITION SUCCESSOR SEW ADDER MPM ADDRESSING I l l i 2 MPCR \NCREMENT [NEXT I m 30 f I082 JlNSTRUOTl0N E 5, AMPCR CONTROL SELECTION (8) l (I) AHT l AMPBR (4) (I) V I (ll o T A A OUT 54 NICROPROGMNMABLE UNIT-l0 [EXTERNAL INTERFAOEZL I lEXIl SHEET CJUF 37 LITERAL ASSIGNMENT msmucnoms FORMATS |23456789l0lli2 64H LITERALTOAMPCR 0 0 LCOMMAND CODE NOT USED INTERNALLY LITERAL VALUE I23456789|0l|l2 GOTOLITERAL I 0 COMMAND CODE NOT USED INTERNALLY JUMPADDRESS |254se1a9|0u|2 e40 LITERALTOB 0 I commmo CODE LITERAL VALUE y V Fig.3

MICROPROGRAM MEMORY ADDRESSING NEXT NEXTCONTENT NEXTCONTENT msmucnow 0F OF ADDRESS MPCR AMPCR STEP MPCR+I MPCR+| x SKIP MPCR+2 MPCR+2 11 SAVE MPCRH MPCR+I MPCR+I JUMP AMPCR AMPCR x X-NOT CHANGED BY SUCCESSOR SPECIFICATION Fig.5

SHEET CM OF 37 CONDITION TEST INSTRUCTION FORMAT I23456T8 9IOIII2 CONDITION SET TRUE FALSE I I I COMMAND CODE FALSE SUCCESSOR OO JUMP OI STEP IO SKIP II SAVE TRUE SUCCESSOR OO JUMP-I28 OI STEP-IO2 IO SKIP-I04 Il SAVE-I06 SET OPERATION OO SET LCI OI SET L02 IO SET LCS II NONE CONDITION SELECT OOO MST-T6 OOI ADV-T8 OIO OII IOO IOI IIO III Fig. 4

EXTERNAL INSTRUCTION FORMAT LITERALTO DEV O O I I IIB LST T4 ABT- 8O LCI 82 LOB-84 LC3-86 EXT-88 LITERAL VALUE (".FEZI1'5131F21S1015 3.878.514

$11511 CSOF 37 LOGIC 111111 11151110011011 I l I 110 112 114 11s 00111111110 CODE 00011111111011 0000 0 0PERATION 11001011501111 0001 Al 0000 x+0+1 0010 112 0001 x+0 0011 115 0010* x+z+1 0100 01110,-- 001111x+z 0101 01111 0100 XEQVBIXBvXB) 0110 01112 0101 11110000011101 0111 1111001101115 0110 x-0 (X+B+1) 100011 005x 0111 x-0-11x+01 100111 111,0Ex 1000 x110110111'101 101011 A2,BEX 1001 x11111101Y01 101111 A3,BEX 101011 x111011z111Tz1 110011 11 0 5 1011* XNANZIYTI 1101 1115 1100 x01101x001 11101 11 1120 1101 x1111001x01 11111101 1155 1110 1111111001 01 1111 x11111111x01 -XSELECT 00 0 01 Al 10 112 11 11s Z=AMPCR. WHEN AMPCR IS NOT SELECTED AS A DESTINATION,THEN AMPGR WILL BE"ZERO" Ii.E.,Z=O) IN ALL OPERATIONS AS A Y SELECT INPUT.

** Y SELECT=B ORZ AS INDICATED 1A 'BEX" INDICATES SERIAL TRANSFER FROM EXTERNAL IN REGISTER TO B REGISTER WHILE ADDER TRANSFERS TO OTHER SPECIFIED REGISTER (IF B,THEN TWO INPUTS ARE O RED).

H "S" INDICATES A ONE-BIT RIGHT SHIFT OF THE DESTINATION REGISTER END OFF,WITH THE MSB BEING FILLED BY THE ADDER OUTPUT.

Fig. 6

SHEET 08 [1F 3? PRESET 6 CLEAR 0 CLOCK 0 DATA 0 7 8 H H H T. 00 Du m BITS 328 BIT8 BIT l2 "71f?" #7325533 3878.514 SREEI 07M 37 CARRYINPUT 1 -254 25s S OUT x mPuT-m 238 YlNPUT-T GARRY mu -m Fig. 9

PRESET COUNT uP D Q LSD I46 CLEAR PRESET I52 T 'Q bNEXT LSD CLEAR Fig. /0 E PRESET I50 T 0 NEXT MSD 3 CLEAR be PREASET I54 T (1% MSD 3 CLEAR CLEARG\ & D

C150 0 EOE wow- I I p I I :5; 1065mm Q Q Q Q o 1 Q Q o zocomwwm @252 $550 EOE 5 158% N\ 9k 212% g Q2; :52 E:

O f ICU I I o SHEU CBUF 37 $-10; L352 22: SE28 SHEET 09 OF 37 OLOOK IN PULSES MOO PULSES LAST PULSE CLOCK OUT PULSES R4 CLOCK IN PULSES MOO PULSES OUTPUT OF NOR GATE 266 OUTPUT OF TERMINAL I54 OUTPUT OE INVERTER I56 IIIIII II OUTPUT OE INVERTER 268 OUTPUT OF NANO GATE 292 SHEET 110F137 LOGICAL ZERO FROM O OUTPUT OF III N .I U DI N VA FROM O OUTPUT OM O OUTPUT Fri R 0 [I0 2IO (BIT I) 2I2IBIT2) T W 00 W W I [L TK n nPu lb I 0 .I R SILG W A N E U 0 0 0 S IL T L UIO DIRCI IP U E .I E GEM HH 5 n. W E WHS I 0 I DI DUB- Inn 2 H SHEET 120F157 OUTPUT 5 VA A VA VA S 2 YA VA H A. A U AP g VA VA VA 2 NW n H H L E B U O! I DW H L L H A B 8 8 2 2 Q m F. E! F H= HIGH LEVEL L= LOW LEVEL X= IRRELEVANT F lg. 28/] SERIAL W saw mgr 3':

OUTPUT NOR GATE BIT l0 BIT 9 o o o 1 |=H|GH sme 0= LOW STATE TRUTH TABLE OUTPUTS OO O O -O O O O O INPUTS XXXXXXXXXXXXXXXO XXXXXXXXXXXXXO XX XXXXXXXXXO XXXXXX XXXXXXXO XXXXXXXX XXXXXO XXXXXXXXXX XXXO XXXXXXXXXXXX XO XXXXXXXXXXXXXX BITS BIT2 BITI MST LCI LST L03 AOV L02 ABT EXT TRUE FALSE VAOO OO OO OO VAOOOO OOOO nUOOOnUAUAUO WHEN USED TO INDICATE AN INPUT, X=IRRELEIIANT T0 LCI FROM NAND GATE BITS BIT4 

1. An apparatus for processing data in accordance with a stored program comprising: memory means for storing a plurality of microinstructions, each of said microinstructions including control information; a serial input bus for receiving information bits to be processed; a serial output bus for transferring processed information bits from said processor; means connected between said buses and coupled to said memory means for accessing at least one of said plurality of microinstructions and providing said control information; and at least one logical unit connected between said buses and responsive to said provided control information received in parallel from said means for accessing for serially performing logical operations on information bits received by said input bus.
 2. An apparatus according to claim 1 wherein said means for accessing includes: control means for generating gating pulses; first means responsive to said control means for selectively retrieving from said memory means said at least one of said plurality of microinstructions from said memory means; and second means coupled to said first means and responsive to certain of said gating pulses for decoding said retrieved instruction.
 3. An apparatus according to claim 2 wherein said first means includes; a unique serial path connecting said input bus to said output bus, said unique path including a first register for receiving address information bits for said memory means; a second register connected between said first register and said memory means for addressing said memory means, said second register receiving address information bits in parallel from said first register; a first parallel path from said second means to said first register, said first parallel path including a selection gate; a second parallel path from said second register to said selection gate; and second control means coupled to said selection gate and said first register and responsive to certain of said provided control information for loading in parallel said first register with decoded information provided by said second means or the contents of said second register to allow repeated retrieval of said at least one of said plurality of microinstructions addressed by said second register or to allow retrieval of a microinstruction specified by said at least one of said plurality of microinstructions or for loading serially said first register with address information bits communicated by said unique serial path.
 4. An apparatus according to claim 1 wherein said logical unit includes; first register means connected to said input bus for storing said received information bits within said apparatus; an arithmetic unit having a first and second input; first gating means connected between said first register means and said arithmetic unit for selectively communicating said stored received information bits to said first input of said arithmetic unit, said arithmetic unit performing arithmetic manipulations on said stored received information bits; second register means connected to said second input of said arithmetic unit for storing said manipulated received information bits within sid apparatus; and second gating means connected between said output bus and said arithmetic unit for selectively communicating said manipulated received information bits from said arithmEtic unit to said output bus or said second register means.
 5. A programmable data processor comprising: a source of microinstructions, each of said microinstructions including control information; a serial input bus for receiving information bits to be processed; a serial output bus for transferring processed information bits; means connected between said buses for selectively retrieving from said source of microinstructions at least one of said plurality of microinstructions; control means coupled to said source of microinstructions and connected between said buses for providing in parallel said control information by decoding said at least one of said plurality of microinstructions; an arithmetic unit; a plurality of serial data paths from said input bus to said output bus, each of said paths including at least one register means and said arithmetic unit; and means coupled to each of said one register means and responsive to said provided control information received in parallel from said control means for transferring said received information bits to said output bus.
 6. In a data processing system including a plurality of input and output registers, an apparatus for processing data in accordance with a stored program comprising: a serial input bus for receiving information bits to be processed; a serial output bus for transferring processed information bits; memory means for storing a plurality of microinstructions, each of said microinstructions having control information; means coupled to said input bus and said memory means for accessing at least one of said plurality of microinstructions; means coupled to said memory means and said plurality of input and output registers and responsive to a portion of said control information provided by said at least one of said plurality of microinstructions for controlling transfer of information bits from said plurality of input registers to said input bus and from said output bus to said plurality of output registers; and a logic unit connected between said buses and coupled to said memory means for performing logical operations on said received information bits responsive to another portion of said control information of said provided at least one of said plurality of microinstructions.
 7. An apparatus for processing data in accordance with a stored program comprising: memory means for storing a plurality of microinstructions, each of said microinstructions including control information, certain of said microinstructions including a data information portion; a serial input bus for receiving information bits to be processed; a serial output bus for transferring processed information bits; address means coupled to said input bus and said memory means for selectively retrieving from said memory means at least one of said plurality of microinstructions, said retrieved at least one of said plurality of microinstructions including said data information portion; decoding means coupled to said memory means for providing said control and said data information of said retrieved at least one of said plurality of microinstructions; first register means coupled to said decoding means for storing said decoded data information; an arithmetic unit; second register means connected between said input bus and said arithmetic unit for storing said received information bits within said apparatus, said arithmetic unit performing arithmetic manipulations on said stored received information bits; and gating means connected between said output bus and said arithmetic unit and said first register means and responsive to said provided control information for selectively gating said stored decoded data information from said first register means or said manipulated received information bits from said arithmetic unit to said output bus.
 8. A microprogrammable processor comprising: a source of microinstructions, each of said microinstructions including control information; a serial input bus for receiving command information and data information bits; a serial output bus for communicating processed data information bits from said processor; command means coupled to said input bus and said source of microinstructions and responsive to said received command information for selecting at least one microinstruction from said source of microinstructions; and a logic unit connected between said buses and coupled to said command means and responsive to said control information of said selected at least one microinstruction for performing logical operations on data information received by said input bus.
 9. A microprogrammable processor comprising: a single semiconductor chip; said chip having fabricated thereon; memory means for storing a plurality of microinstructions, each of said microinstructions including control information; a serial input bus for receiving information bits to be processed; a serial output bus for communicating processed information bits from said processor; address means connected to said input bus and said memory means for selectively retrieving from said memory means individual ones of said microinstructions; and a logic unit connected between said serial buses and coupled to said memory means for performing logical operations on said received information bits in accordance with said control information from each of said individual ones of said microinstructions. 